`timescale 1ns/1ns


module tb_asfifo();
   parameter data_width = 8;
   parameter address_width = 6;
   
   wire[data_width-1:0] data_out;
   wire 				empty, full;

   reg 					read_en, write_en;
   reg [data_width-1:0] data_in;

   reg 					clk_read, clk_write;
   reg 					rst;
 					
		
asfifo #(
		 .data_width(data_width),
		 .address_width(address_width)
		 ) asfifo_inst (
						.data_out(data_out),
						.empty(empty),
						.read_en(read_en),
						.clk_read(clk_read),
						
						.data_in(data_in),
						.full(full),
						.write_en(write_en),
						.clk_write(clk_write),
						
						.rst(rst)
						);
   
   always #150 clk_read = ~clk_read;
   always #10 clk_write = ~clk_write;

//some temp variables
   integer 			 i;
   
   initial begin
	  rst = 1;clk_read = 0; clk_write = 0;

	  #25 rst = 0; 
	  read_en = 1;
	  write_en = 1;
	  data_in = 8'h12;

	 for(i=0;i<8'hff;i=i+2)
	   #20 data_in = i;
   end
endmodule // tb_asfifo

		 
   

			
			
   






